Non-volatile memory devices are used in applications requiring the storing of information that has to be retained even when the memory devices are not powered. Generally, each memory device includes a matrix of memory cells based on floating-gate MOS storage transistors; each storage transistor has a threshold voltage that may be set (according to an electric charge in its floating gate) to different levels representing corresponding logic values.
For example, in Electrical Erasable and Programmable Read-Only Memories (E2PROMs) each storage transistor may be both programmed (by injecting electric charge into its floating gate) and erased (by removing electric charge from its floating gate) individually—thanks to the use of a set of MOS selection transistors that selectively apply the required voltages to the corresponding storage transistor (with a quite complex structure that may limit the capacity of the E2PROMs to a few kilobytes). On the other hand, flash memories have a simple structure that allows obtaining very high capacities thereof, for example, up to some gigabytes, thanks to the grouping of the memory cells in sectors each integrated in a common well of semiconductor material without any selection transistor (with the flash memory cells being erased by sector).
In both cases, a production process of the memory devices substantially differs from a standard one (for example, in CMOS-technology). Indeed, the storage transistors require an additional polysilicon layer to define their floating gates (besides the one used to define their control gates as in CMOS transistors). This difference adds design complexity, which may significantly increases the manufacturing cost of the memory devices (e.g., on the order of 30% with respect to standard CMOS devices).
In order to solve these problems, Few Time Programmable (FTP) or Cost-Effective memories have been proposed in the last years. In the FTP memories, the memory cells are again grouped in sectors (integrated in corresponding wells). However, the storage transistor of each memory cell now has a distinct control gate region being capacitively coupled with its floating gate; therefore, the FTP memories require a single polysilicon layer, so that they may be manufactured with the standard CMOS production process.
The FTP memories known in the art are generally based on a so-called emitter structure. Particularly, in the emitter-FTP memories, each memory cell includes, in addition to the storage transistor, an MOS selection transistor (being used to select the memory cell for its reading), and a stray BJT injection transistor (being used to implement its programming). The memory cells are programmed by hot electron injection (very fast through their injection transistors) and they are erased by the Fowler-Nordheim effect. An example of emitter-FTP memory is described in U.S. Pat. No. 6,876,033, which is herein incorporated by reference.
This makes the FTP memories very attractive for embedding memories of small capacity (up to some Kbytes) into CMOS devices; indeed, in this case it is possible to add the FTP memories at low cost and with low overhead (since they do not require complex re-design and test operations).
However, FTP-memories have to be erased at the sector level. Moreover, they require very high voltages (both positive and negative) for programming and erasing the memory cells, and high currents for their programming. Particularly, in the emitter-FTP memories, the injection transistors have a stray structure; therefore, the injection transistors often cannot be characterized accurately, and thus they may have to be over-dimensioned to ensure the required performance in every operating condition. Therefore, the currents that are used during the programming of the memory cells may further increase (e.g., up to approximately 0.1-5 mA). This requires very complex charge pumps to generate the required high voltages (from a lower power supply voltage), and at the same time provide the required high currents. In addition, the high voltages and currents involve large power consumption. These high currents also limit a programming parallelism (for example, to 8 memory cells). Moreover, during the erasing of a selected sector, the high voltages applied to its memory cells in part propagate to the other memory cells that are capacitively coupled thereto. As a result, these memory cells are subject to an electric stress that may cause a loss of electric charge in the floating gates of their storage transistors, with an undesired erasing of the memory cells after repeated erasing operations. This limits the data retention of the memory cells, and the number of erasing operations that may be withstood (of the order of a few thousands) before the cells may be rendered inoperable.